1. Field of the Invention
This invention relates to digital-to-analog converters of the CMOS type. More particularly, this invention relates to minimizing leakage current in such converters.
2. Description of the Prior Art
CMOS D/A converters have been available commercially for quite some time, and provide important advantageous features. Referring now to FIG. 1, conventional converters of the CMOS type include a thin-film R-2R ladder network 10 the shunt resistors of which are connected to N- channel CMOS switch-pairs 12A/B; 14A/B; etc. The individual switches of each pair are complementarily driven so that one switch is off while the other is on, and vice versa. The switches typically have a voltage across them of 10 mV for a 10 V reference voltage and a 10 k.OMEGA.-20 k.OMEGA. ladder network.
There are three commonly-used configurations of conventional CMOS D/A converters. In order to explain leakage current, each one of these configurations will be examined separately.
Referring first to FIG. 2, the converter shown there comprises three separate lines for I.sub.OUT1, I.sub.OUT2 and AGND (analog ground). The ladder termination resistor 16 is tied to AGND. When an all zero's code is applied to the converter, all of the current in the R-2R ladder 10 (except for the one bit of current flowing through the ladder termination resistor to AGND) is steered to the I.sub.OUT2 terminal. Ideally no current should under these conditions flow to the I.sub.OUT1 terminal. However, in practice a finite current does flow in the I.sub.OUT1 terminal and is know as the leakage current.
When an all one's code is applied to the converter of FIG. 2, all of the current in the R-2R ladder (except, again, for the one bit of current through the ladder termination resistor to AGND) is steered to the I.sub.OUT1 terminal. Any current flowing in the I.sub.OUT2 terminal is defined as leakage current.
Referring now to FIG. 3, again there are three separate lines for I.sub.OUT1, I.sub.OUT2 and AGND. The ladder termination resistor 16 now is tied to I.sub.OUT2. When an all zero's code is applied to the D/A converter all of the current in the R-2R ladder is steered to the I.sub.OUT2 terminal, and any current flowing in the I.sub.OUT1 terminal is defined as leakage current.
When an all one's code is applied to the converter of FIG. 3, all of the current in the R-2R ladder (except for the one bit of current flowing through the ladder termination resistor to I.sub.OUT2) is steered to the I.sub.OUT1 terminal. Because of this one bit of current flowing along the I.sub.OUT2 line, it is not possible to measure leakage current. Hence, leakage current is only defined along the I.sub.OUT1 line for an input code of all zeros.
Referring now to FIG. 4, there is an I.sub.OUT line and an AGND line, where AGND incorporates AGND and I.sub.OUT2 of FIGS. 2 and 3. The ladder termination resistor 16 is tied to AGND. When an all zero's code is applied to the D/A converter, all the current in the R-2R ladder is steered to the AGND terminal. Any current flowing in the I.sub.OUT line is defined as leakage current.
Leakage current, as defined above for the circuit configurations of FIGS. 2 through 4, causes errors in the D/A transfer characteristic, particularly at temperatures greater than 100.degree. C. where the effect is most pronounced. Thus it is desired to reduce such errors.
The leakage current described above actually comprise two separate components which arise for different reasons. To explain this, reference is made to FIG. 5 which shows somewhat schematically the IC structural arrangement of the switches 12A/B for a conventional CMOS DAC. The N- substrate 20 normally is at the most positive supply voltage (5 V to 15 V). The P- well 22 is at zero potential (ground). Leakage current in such a structure comprises the following two components:
(a) Subthreshold leakage current from the R-2R ladder across the "off" switch to I.sub.OUT1 or I.sub.OUT2, depending on along which line the leakage current is being measured. This is shown as I.sub.1.
(b) Collector-emitter leakage current of the substrate NPN bipolar transistor with grounded base. The transistor is formed by a reverse-biased diode from the N- substrate (collector) to the P- well (base), and a diode from the P- well (base) to the N+ source diffusion (emitter). The N+ source diffusion (emitter) referred to is either to I.sub.OUT1 or I.sub.OUT2, depending on along which line the leakage current is being measured. This is shown as I.sub.2.
This invention is directed to means and techniques for eliminating or significantly minimizing the leakage currents described above.